1. Field of the Invention
The present invention relates to an integrated circuit having a complementary (e.g., CMOS) input buffer.
2. Description of the Prior Art
Integrated circuits (ICs) use one or more input buffers to interface with external circuitry that supplies digital or analog signals to the IC. In the case of CMOS (from Complementary Metal Oxide Semiconductor) integrated circuits, the input buffer typically takes the form shown in FIG. 1. An input voltage V.sub.in is applied to the gates of p-channel pull-up transistor 11 and n-channel pull-down transistor 12, which form an input inverter complementary pair. The drains of input transistors 11 and 12 are coupled to common node 13, which drives the gates of the output inverter complementary pair, transistors 14 and 15. This output inverter is usually included to provide additional capability to chive various other circuitry on the IC from the buffer output node 16. One criteria of buffer operation is propagation delay, which is the difference in time that the input crosses the switching threshold of the input inverter pair (typically about 1.5 volts) to the time the output (node 16) crosses the voltage of 1/2 V.sub.DD (typically about 2.5 volts). Another criteria is power consumption, which depends in large part upon the current I.sub.1 that flows through the input inverter.
In the case of buffers designed to receive transistor-transistor logic (TTL) voltage levels, the current I.sub.1 may become undesirably large. This is because the TTL logic levels are, at worst case, 0.8 volts (low) or 2.0 volts (high). These voltages are usually above the conduction thresholds of CMOS transistors 11 and 12. That is, the p-channel input transistor (I 1) and n-channel input transistor (12) may both be conducting at V.sub.in =0.8 volts, and typically even more conducting at V.sub.in =2.0 volts. Therefore, since DC voltages may be present at these levels when TTL input signals are supplied, a relatively large current I.sub.1 may flow, causing undesirably high power consumption by the input buffer. One technique of limiting this current flow is to make the input transistors smaller, which increases their "on" resistance. However, that has the undesirable effect of limiting the speed of the input transistors. Hence, a solution to the problem has been sought by other means.
One technique that has been successfully adopted in practice is shown in U.S. Pat. No. 672,243 co-assigned herewith. That technique makes use of a transition detector to control a voltage boosting means connected to the input of the first inverter, and may be considered a "feed-forward" technique. However, that technique requires a relatively large number of additional transistors. In another approach, a voltage-dropping transistor is inserted between the positive power supply (V.sub.DD) and the p-channel input transistor; see, for example, U.S. Pat. No. 4,471,242. The reduced operating voltage prevents the p-channel input transistor from turning on when the lowest level of a logic "1" is present. However, that approach typically results in a significant reduction of operating speed.